1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, a semiconductor device having bump pads.
2. Description of the Related Art
Semiconductor device designing, packaging fabrication and software may be key technologies that rapidly develop electronic devices. R&D in the field of the designing has attained high-level specification of the semiconductor device, for example, a line width of under micrometer, cells of over a million, an operation of high speed and a heat sink of large capacity. However, the semiconductor device is a relatively low-level in the field of the packaging, which limits its overall performance. For example, over 50 percent of overall signal delay of the semiconductor device may be caused in chip-to-chip packaging. It may increase to over 80 percent as the size of the device become larger, which places importance on the packaging technology for overall performance of the semiconductor device.
The emergence of digital network information era triggers growth of digital appliances and personal digital devices, in which a smaller size, higher performance and function and a lower cost are required to semiconductor devices.
Among packaging technologies, the requirements may be met by chip on chip (CoC) packaging, where a memory chip of large capacity and logic IC may be put into a package with high data transmission speed therebetween. Other packaging technologies putting the memory chip and the logic IC together into one package such as system on chip (SoC) and system in package (SiP) may not achieve the memory chip with both of the large capacity and high speed, whereas the CoC packaging may do, which may reduce manufacturing cost more than a merged DRAM technology.
The reason why the CoC packaging may achieve both of the large capacity and high speed is that the memory chip and the logic IC are stacked and connected through bump pads. According to the CoC packaging, individual memory chip may eliminate capacity limitation of the merged DRAM and increasing bit width and number of bump pads may raise the data transmission speed. The diameter of a bump pad is dozens of micrometers, which makes it easier to raise operation frequency of the semiconductor device due to good electrical characteristics of the bump pad such as low resistance, inductance, parasitic capacitance and so forth. A bump pad is a conductive bump for directly connecting chips.
For connecting the memory chip and the logic IC through the CoC packaging technology, bump pads are formed on each of the memory chip and the logic IC and the chips are put together through the formed bump pad to become one chip. After completion of the CoC packaging, operability of the memory chip is tested with data inputted and outputted through the bump pad.
FIG. 1 is a circuit diagram illustrating a bump pad test of a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device includes 512 bump pads Q<0> to Q<511>, 8 probe pads DQ<0> to DQ<7>, 512 bump input and output units 10<0> to 10<511>, 8 probe input and output units 20<0> to 20<7>, 512 global input and output lines GIO<0> to GIO<511>, and 8 test data mux units MUX<0> to MUX<7>.
FIG. 1 shows as an example specific number of elements, for example the 512 bump pads, 8 probe pads, 512 bump input and output units, 512 global input and output lines and 8 test data mux units, which may be differently implemented depending on the circuit design.
The 512 bump input and output units 10<0> to 10<511> input or output 512 data DATA<0> to DATA<511> in parallel through the 512 bump pads Q<0> to Q<511>. The 512 bump input and output units 10<0> to 10<511> communicate the 512 data DATA<0> to DATA<511> with internal circuits (not illustrated) through the 512 global input and output ones GIO<0> to GIO<511>.
The 512 bump input and output units 10<0> to 10<511> and the 512 bump pads Q<0> to Q<511> are classified into 4 channels, each of which includes 128 bump input and output units and 128 bump pads, and individually performs a data input and output operation.
Channel A CH A includes first to 128th bump pads Q<0> to Q<127> and first to 128th bump input and output units 10<0> to 10<127>. Channel B CH B includes 129th to 256th bump pads Q<128> to Q<255> and 129th to 256th bump input and output units 10<128> to 10<255>. Channel C CH C includes 257th to 384th bump pads Q<256> to Q<383> and 257th to 384th bump input and output units 10<256> to 10<383>. Channel D CH D includes 385th to 512nd bump pads Q<384> to Q<511> and 385th to 512nd bump input and output units 10<384> to 10<511>.
Each of the 4 channels CH A to CH D has independence of data input and output. For example, 128 data DATA<0> to DATA<127> may be input to the channel A CH A while 128 data DATA<128> to DATA<255> are output from the channel B CH B. For example, 128 data DATA<128> to DATA<255> may be input to the channel B CH B while 128 data DATA<384> to DATA<511> are output from the channel D CH D.
The 512 bump input and output units 10<0> to 10<511> input or output the 512 data DATA<0> to DATA<511> through the 512 bump pads Q<0> to Q<511> that are formed by the CoC packaging technology and thus the size of each of 512 bump pads Q<0> to Q<511> is very small, which makes it difficult to input and output test of the 512 data DATA<0> to DATA<511> with the 512 bump pads Q<0> to Q<511> and the 512 bump input and output units 10<0> to 10<511> through a test probe of the conventional semiconductor test device.
In the conventional semiconductor device, 8 test data TDATA<0> to TDATA<7> are input through the 8 probe pads DQ<0> to DQ<7> and 8 probe input and output units 20<0> to 20<7>. The 8 test data TDATA<0> to TDATA<7> are repeatedly transmitted to the 512 global input and output lines GIO<0> to GIO<511> to test the data input and output operation between the 512 global input and output lines GIO<0> to GIO<511> and the internal circuits.
In detail, the 8 probe input and output units 20<0> to 20<7> input or output the 8 test data TDATA<0> to TDATA<7> in parallel through the 8 probe pads DQ<0> to DQ<7>. The 128 global input and output lines corresponding to one of the 4 channels CH A to CH D are divided into 8 groups, which are connected to the 8 probe input and output units 20<0> to 20<7> through the 8 test data mux units MUX<0> to MUX<7> respectively.
For the channel A CH A, the corresponding 128 global input and output lines GIO<0> to GIO<127> are divided into 8 groups GIO<0:15>, GIO<16:31>, GIO<32:47>, GIO<48:63>, GIO<64:79>, GIO<80:95>, GIO<96:111> and GIO<112:127>, which are connected to the 8 probe input and output units 20<0> to 20<7> and 8 probe pads DQ<0> to DQ<7> through the 8 test data mux units MUX<0> to MUX<7> respectively.
For the channel B CH B, the corresponding 128 global input and output lines GIO<128> to GIO<255> are divided into 8 groups GIO<128:143>, GIO<144:159>, GIO<160:175>, GIO<176:191>, GIO<192:207>, GIO<208:223>, GIO<224:239> and GIO<240:255>, which are connected to the 8 probe input and output units 20<0> to 20<7> and the 8 probe pads DQ<0> to DQ<7> through the 8 test data mux units MUX<0> to MUX<7>, respectively.
For the channel C CH C, the corresponding 128 global input and output lines GIO<256> to GIO<383> are divided into 8 groups GIO<256:271>, GIO<272:287>, GIO<288:303>, GIO<304:319>, GIO<320:335>, GIO<336:351>, GIO<352:367> and GIO<368:383>, which are connected to the 8 probe input and output units 20<0> to 20<7> and the 8 probe pads DQ<0> to DQ<7> through the 8 test data mux units MUX<0> to MUX<7>, respectively.
For the channel D CH D, the corresponding 128 global input and output lines GIO<384> to GIO<511> are divided into 8 groups GIO<384:399>, GIO<400:415>, GIO<416:431>, GIO<432:447>, GIO<448:463>, GIO<464:479>, GIO<480:495> and GIO<496:511>, which are connected to the 8 probe input and output units 20<0> to 20<7> and the 8 probe pads DQ<0> to DQ<7> through the 8 test data mux units MUX<0> to MUX<7> respectively.
As such, the 512 global input and output lines are classified into 4 groups corresponding to the 4 channels CH A to CH D, respectively, and the each group of 128 global input and output lines are divided into 8 groups connected to the 8 probe input and output units 20<0> to 20<7> and the 8 probe pads DQ<0> to DQ<7> through the 8 test data mux units MUX<0> to MUX<7>, respectively.
The 8 test data TDATA<0> to TDATA<7> are selected 16 times and transmitted through the 8 test data mux units MUX<0> to MUX<7> to each of the 4 channels CH A to CH D, that is, each of the global input and output lines GIO<0:127>, GIO<128:255>, GIO<256:383> and GIO<384:511> corresponding to the respective channels CH A to CH D.
In other words, the 8 probe input and output units 20<0> to 20<7> sequentially operate 16 times, each time select 8 lines from the 128 global input and output lines GIO<0:127>, GIO<128:255>, GIO<256:383> or GIO<384:511>, and transmit the 8 test data TDATA<0> to TDATA<7> to the selected 8 global input and output lines from the 128 global input and output lines GIO<0:127>, GIO<128:255>, GIO<256:383> or GIO<384:511>.
However in the conventional semiconductor device, the 4 channels CH A to CH D share the 8 probe pads DQ<0> to DQ<7>, the 8 probe input and output units 20<0> to 20<7> and the 8 test data mux units MUX<0> to MUX<7>, and thus the 8 test data TDATA<0> to TDATA<7> may not be inputted to the 4 channels CH A to CH D at the same time.
For example, the 8 test data TDATA<0> to TDATA<7> may not be input to the 3 channels CH B to CH D while the 8 test data TDATA<0> to TDATA<7> is being input to the channel A CH A through the 128 global input and output lines GIO<0> to GIO<127> corresponding to the channel A CH A.
Therefore, it is by time-division that the 8 test data TDATA<0> to TDATA<7> are input to each of the global input and output lines GIO<0:127>, GIO<128:255>, GIO<256:383> and GIO<384:511> corresponding to the respective channels CH A to CH D through the shared 8 probe pads DQ<0> to DQ<7>, the shared 8 probe input and output units 20<0> to 20<7> and the shared 8 test data mux units MUX<0> to MUX<7> which may lead to increase of test time.
Further, the conventional semiconductor device does not include a mechanism for allowing data to be input or output through the 512 bump pads Q<0> to Q<511> and the 512 bump input and output units 10<0> to 10<511>. Even though the data may be input to or output from the 512 global input and output lines GIO<0> to GIO<511> through the 8 probe pads DQ<0> to DQ<7> and the 8 probe input and output units 20<0> to 20<7>, the data may not be tested through the 512 bump pads Q<0> to Q<511> and the 512 bump input and output units 10<0> to 10<511>.
Thus, in the conventional semiconductor device at the wafer level, the 512 bump pads Q<0> to Q<511> and the 512 bump input and output units 10<0> to 10<511> may not be tested. The test may be performed after the 512 bump pads Q<0> to Q<511> are connected to external balls or pads at package level.
Such test may not detect a bump pad defect of the semiconductor device at the wafer test level, which is inefficient and leads to high cost of the test.